1. Field of the Related Art
The present invention relates to a semiconductor integrated circuit, a method of placing elements formed thereon, and a program for placing the elements, and more particularly to a technique for placing on-chip capacitors for controlling the influence of noise in placement design of LSI design CAD.
2. Description of the Related Art
In the design of a semiconductor integrated circuit (also referred to as LSI), small circuits such as NAND, NOR, inverter circuits, and the like called function blocks that perform basic operations are placed in an LSI (large scale integrated circuit) to be produced on a computer program, and routings among the circuits are connected to produce basic data of a mask used for semiconductor manufacturing. This process is referred to as placement and routing processing.
The placement and routing processing is performed mainly by a routing program and a placement program. Conventional placement programs have performed placement with the purpose of putting routing-caused delay and routing space within target values.
However, recent, very fast LSIs are afflicted with the generation of noise during operation of function blocks. To control the influence of noise, it is effective to place on-chip capacitors in spaces inside an LSI. The on-chip capacitors are capacitors employing PN junction capacitances and gate capacitances.
A method of placing on-chip capacitances in LSI design is described by an invention of JP-A 168177/1999. Although on-chip capacitors produced by the invention are placed in spaces of a placement result decided only with delay constraints, they are not placed with consideration to function blocks prone to generate noise and function blocks susceptible to noise.
The on-chip capacitors exhibit higher effects when they are placed nearer to the vicinity of noise source and the vicinity of function blocks susceptible to noise. However, since conventional placement programs do not take the generation of noise into account, it has been impossible to effectively place the on-chip capacitors in the vicinity of a noise source and function blocks susceptible to noise.
According to the invention in JP-A 168177/1999, as the number of function blocks mounted in a placement area increases, tiny spaces will occur between the function blocks. Since an on-chip capacitor requires a space of some width, it is difficult to effectively place on-chip capacitors in an environment interspersed with tiny spaces.